1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device that controls skews of a plurality of input signals.
2. Description of the Related Art
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) receives a plurality of signals such as commands, addresses, or data from an exterior, and performs a write operation or a read operation. In the write operation, the semiconductor memory device receives addresses and data and stores the data in a memory cell corresponding to the addresses. Furthermore, in the read operation, the semiconductor memory device outputs the data stored in the memory cell corresponding to the addresses to an exterior.
Meanwhile, recently, since a semiconductor memory device shows an improvement toward a high speed and large capacity, the amount of data to be processed at a time is gradually increased. The increase in the amount of data capable of being processed is indebted to not only high operating frequency but a parallel data interface. That is, when a large amount of data is input or output through a plurality of data pads at a time, it is possible to perform an operation of processing a larger amount of data.
FIG. 1 is a block diagram illustrating a partial configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes first to nth delay units 111_1 to 111—n, a data storage unit 112, and a skew control unit 113. The semiconductor memory device receives data DQ1 to DQn, a plurality of addresses ADD, and a plurality of commands CMD through corresponding pads, and performs a write operation or a read operation.
The first to nth delay units 111_1 to 111—n reflect times, which correspond to first to nth delay control codes CTR1<1:m> to CTRn<1:m>, in the data DQ1 to DQn input through a plurality of data pads, and output data to the data storage unit 112. The data storage unit 112 receives and stores the data DQ1 to DQn in the write operation, and outputs the stored data to the first to nth delay units 111_1 to 111—n in the read operation. The skew control unit 113 generates the first to nth delay control codes CTR1<1:m> to CTRn<1:m> based on the addresses ADD and the commands CMD.
The first to nth delay units 111_1 to 111—n compensate for skews to be reflected in the data DQ1 to DQn in response to the first to nth delay control codes CTR1<1:m> to CTRn<1:m>.
In more detail, even though the data DQ1 to DQn input from an exterior is input to corresponding data pads at substantially the same time point, different skews due to different signal transfer paths are reflected in the data DQ1 to DQn. Therefore, the data DQ1 to DQn are transferred to the data storage unit 112 at different time points, and circuits for compensating for the skews are the first to nth delay units 111_1 to 111—n. That is, the first to nth delay units 111_1 to 111—n set delay amounts according to the first to nth delay control codes CTR1<1:m> to CTRn<1:m>, and the data DQ1 to DQn is delayed by corresponding delay amounts and is transferred to the data storage unit 112. Through such a delay compensating operation, the data DQ1 to DQn may be transferred to the data storage unit 112 at substantially the same time point.
As described above, the first to nth delay units 111_1 to 111—n determine delay amounts based on the first to nth delay control codes CTR1<1:m> to CTRn<1:m>, and the skew control unit 113 generates the first to nth delay control codes CTR1<1:m> to CTRn<1:m> in response to a plurality of addresses ADD and a plurality of commands CMD input in a test operation mode.
Meanwhile, as a semiconductor memory device shows a tendency toward a high speed and large capacity, the number of the data DQ1 to DQn is gradually increased, and thus the number of delay units corresponding to the data DQ1 to DQn is also increased. Therefore, the number of the first to nth delay control codes CTR1<1:m> to CTRn<1:m> for controlling the first to nth delay units 111_1 to 111—n is also increased. An increase in the number of the first to nth delay control codes CTR1<1:m> to CTRn<1:m> leads to an increase in the number of transfer lines for transferring the delay control codes, resulting in a burden in a layout design.
Furthermore, in order to finely control times of the first to nth delay units 111_1 to 111—n, the bit number of the first to nth delay control codes CTR1<1:m> to CTRn 1:m> needs to be larger than m. The first to nth delay control codes CTR1 1:m> to CTRn<1:m> are transferred through relatively long signal lines. That is, when the bit number of the delay control codes is increased, the number of the long signal lines is also increased, resulting in a burden in the layout design.